Project Suggestions

These projects must be constructed and using a flit level simulator. In some cases, VHDL/Verilog simulation may be acceptable. Projects may be proposed as single or multi-person depending on the scope, but multi-person requires advance discussions and approval – do not wait until the last week!

  1. Techniques for On-Demand Congestion Management: Simple techniques can be used to detect and propagate congestion information in a network. Use this information to dynamically adjust buffer capacity and link widths. The goal is power efficient operation.
  2. Strategies for cycle-accurate parallel simulation environment: Execution environment is clusters. Goal is to scale systems sizes that can be reliably simulated, to at least fewthousand switches. A parallel simulation kernel will be provided.
  3. Quality of Service Guarantees: Implement techniques for providing quality of service guarantees, e.g., guaranteed latency bounds or bandwidth.
  4. Impact of Process, Voltage, and Temperature (PVT) Variations on Network Links: Using established models of PVT variations and known optimal link designs (use of repeaters, pipelined links) assess the impact of PVT variations on link and network performance. This will involve developing SPICE models
  5. Reliable Switching and Flow Control Protocols: Study and evaluate the problem of making low level flow control protocols and associated switching mechanisms reliable.
  6. Optimizations that use Ultra-wide Network Links: On-Chip networks are encouraged to be wide and of low dimension. Increasing utilization of the links can be achieved by partitioning links and packing messages into single link cycles. Evaluate the gains that can be made using this approach.
  7. Support for System Wide Functions – Network Partitioning: Evaluate architectural support for network partitioning in support of virtual machines.
  8. Heterogeneous Networks: Networks may not be homogenous. For example, different parts of the network may have different switch sizes or link widths. Case in point is near the memory controllers where there bursty congestion.
  9. Integrating Memory Controllers and Networks: Provide an algorithm for optimized placement of memory controllers and a detailed simulation evaluation of its placement.
  10. Full System Simulation: This is a two person project. It involves using the Manifold full system simulator to look at the effects of standard benchmarks on a flit level simulator. In particular exploring multiple topologies for on-chip high core count chip mulyiprocessors.
  11. Networks for 3D ICs: Evaluate candidate networks for 3D chip stacks.