ECE 8813a Spring 2012

ECE 8813a Spring 2012

Design and Analysis of Multiprocessor Interconnection Networks

Spring 2012

Prerequisite: ECE 6100: Advanced Computer Architecture

Course Objective: Cover the core architectural concepts of modern multiprocessor interconnection networks, both on-chip and off-chip, and the associated formal methods for the design of deadlock-free and livelock free routing protocols. Coverage includes recent standards, and the latest papers on router microarchitecture, network optimization, performance optimization, and technology dependence

Course Material: Lecture material will be drawn from the following sources
“Interconnection Networks: An Engineering Approach”, J. Duato, S. Yalamanchili and L. Ni, Morgan Kaufmann (pubs.), 2003
“Principles and Practices and Interconnection Networks,” W. J. Dally and B. Towles, Morgan Kaufmann (pubs).
Journal and conference papers

Course Syllabus: Syllabus
Instructor: Sudhakar Yalamanchili
Contact Information: KACB 2316, Email:, Tel: 404-894-2940
Fall 2012 Office Hours: MW 6-7, W 3-4, Other times by appointment, email most anytime

Exam Schedule:
Exam I (20%): February 22nd, 2012

Assignment Schedule:
Projects are to be executed individually. If you wish to propose a group project, the level of effort must be commensurate with the number of people. Please discuss this early in the semester with me. A timeline is contained in the introductory lecture. Some suggestions for projects can be found here

Students are responsible for all material covered in class, including changes in exam schedules announced in class. Make-up exams will be considered only if the student informs the instructor of the absence prior to the exam date, or, when prior information was not possible, immediately following the exam. Make-up exams are not guaranteed to be the same as the exam given in class.

Academic Honesty:
Although students are encouraged strongly to work together to learn the course material, all students are expected to complete assignments and exams individually, following all instructions stated in conjunction with the exam. All conduct in this course will be governed by the Georgia Tech honor code. Additionally, it is expected that students will respect their peers and the instructor such that no one takes unfair advantage of anyone else associated with the course. Any suspected cases of academic dishonesty will be reported to the Dean of Students for further action.

Schedule of Lectures
Note that IEEE/ACM papers are accessed through T-Square. These are also electronically available through the library and are governed by copyrights that you are responsible for honoring.

Module Last Update Lecture Sources of Lecture Material
1 1/20/2012 Course Overview & Introduction (introduction.pdf, introduction.ppt)

Duato: 1.1-1.4

Papers on Tsquare

2 1/20/2012 Flow Control (FlowControl.pdf, FlowControl.ppt)

Duato: 2.1, 2.2

Papers on Tsquare

3 1/20/2012 Switching Techniques (Switching.pdf, switching.ppt)

Duato: 2.3-2.8

Papers on Tsquare

4 1/20/2012 Topologies-I (topologies-I.pdf, topologies-I.ppt), Topologies-II (topologies-II.pdf, topologies-II.ppt)

Duato: 1.4-1.9

Papers on Tsquare

5  2/17/2012

Deadlock and Livelock – I (deadlock-I.ppt, deadlock-I.pdf),

Deadlock and Livelock – II (deadlock-II.pptdeadlock-II.pdf)

Duato:Chapter 3

Papers on Tsquare

6  3/4/2012 Router Architectures (SingleSwitch.ppt, SingleSwitch.pdf) Papers on Tsquare
7  4/4/2012 Routing Algorithms  (routing.pptx, routing.pdf) Papers on Tsquare
8  4/2/2012 Network Optimization (optimization.ppt, optimization.pdf)

Duato: Chapter 7.1

Papers on Tsquare

9 System Impact of Networks TBD
10 Case Studies TBD